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[Other] CPU

Description: verilog 实现的CPU，用Modelsim SE 6.2b 创建的工程，包含测试文件。- CPU of verilog implementation
Platform: | Size: 72704 | Author: DHC | Hits:

[VHDL-FPGA-Verilog] cpu_16bit

Description: design cpu 16 bits by verilog HDL.
Platform: | Size: 1024 | Author: tommy | Hits:

[VHDL-FPGA-Verilog] alu

Description: mcu，risc cpu Verilog源代码-mcu，risc cpu Verilog
Platform: | Size: 4096 | Author: yzhang | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[VHDL-FPGA-Verilog] CPU

Description: Cpu with 8 bits in VHDL verilog Code
Platform: | Size: 2048 | Author: guilherme | Hits:

[VHDL-FPGA-Verilog] KD-CPU

Description: 计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.
Platform: | Size: 503808 | Author: 张鸿云 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
Platform: | Size: 1735680 | Author: era | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
Platform: | Size: 19456 | Author: qc | Hits:

[VHDL-FPGA-Verilog] cpu-kongzhi

Description: 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-clock with Verilog HDL CPU controller, the ISE on the waveform simulation and FPGA implementation.
Platform: | Size: 1024 | Author: dino | Hits:

[VHDL-FPGA-Verilog] CPU_Verilog

Description: 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
Platform: | Size: 12288 | Author: fairchildfzc | Hits:

[VHDL-FPGA-Verilog] hamming

Description: verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)
Platform: | Size: 49736704 | Author: 嵩山独坐 | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU-master

Description: 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)
Platform: | Size: 57344 | Author: 9901tzh | Hits:

[VHDL-FPGA-Verilog] mips-cpu-master

Description: MIPS Implementation in Verilog. Full source code!
Platform: | Size: 39936 | Author: loox_dg | Hits:

[VHDL-FPGA-Verilog] Verilog HDL使用中该注意的问题及一些模块代码

Description: cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
Platform: | Size: 200704 | Author: momotou | Hits:

[VHDL-FPGA-Verilog] CPU-Pipeline

Description: 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
Platform: | Size: 14336 | Author: Si Cheng | Hits:

[VHDL-FPGA-Verilog] 实验九 计算机核心（CPU+RAM）的设计与实现

Description: 计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)
Platform: | Size: 3360768 | Author: 丁丫头 | Hits:
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